1. Field of the Invention
The present invention relates to methodology of locating faults in logic integrated circuits and, more particularly, to methodology of locating faults of scan chains in logic integrated circuits.
2. Description of the Related Art
In order to satisfy performance demands of computers, communications, and consumer electronics, the semiconductor industry starts developing technology related to integrating an entire, complicated system onto a single chip. Along with continuous progress of the semiconductor processing technology, a single chip is able to accommodate more and more logic gates. It is expected that such a technical innovation trend will continue until the nearest future. As a result of the dramatic increase of the complication level on the chip, it is more difficult to analyze possible faults existing in the chip.
In the testing of a logic integrated circuit, scanning is a very effective design for test, having very high fault coverage. The testing mode is executed without interfering normal operations of the logic integrated circuits. Scan chains consisting of series-connected flip-flops are utilized to detect the faults in the integrated circuits. Hereinafter is described in brief a method of analyzing faults in a logic integrated circuit by the scanning method with reference to FIG. 1.
A logic integrated circuit 1 includes a number of functional circuit modules 13. In order to test the logic integrated circuit 1, a plurality of scan chains 121, 122, and 123 are designed therein. The scan chains 121, 122, and 123 consist of series of flip-flops 1211, 1221, and 1231, respectively. Each of the flip-flops 1211, 1221, and 1231 is connected to a corresponding one of the functional circuit modules 13. During the testing, each of the functional circuit modules 13 transfers a value of logic 0 or logic 1 to the correspondingly connected one of the flip-flops 1211 of the scan chain 121. Next, the series of flip-flops 1211 output a testing sequence 1212 one digit by one digit. Similarly, the scan chains 122 and 123 output the testing sequences 1222 and 1232, respectively. Each of the testing sequences 1212, 1222, and 1232 is compared with a predetermined correct sequence for identifying any inconsistence in each of the testing sequences 1212, 1222, and 1232. With reference to the compared result, the faults in the logic integrated circuit 1 can be located.
For the above-mentioned method of analyzing faults, a reset circuit 11 must be provided in the logic integrated circuit 1 for setting the initial states of the flip-flops as either logic 0 states or logic 1 states, usually as logic 0 states. Along with the increase of the chip complication level, the number of the scan chains must be added in order to effectively locate the faults of the functional circuit modules 13. Therefore, the number of the reset circuits also increases along with the increase of the scan chains. Some of the reset circuits have special functions. However, some of the reset circuits are merely for the purpose of resetting the initial states of the flip-flops. Such reset circuits inevitably occupy certain area of the chip, causing that the chip size reduction is restricted and the chip yield per wafer is suppressed.